[Oberon] Oberon ->(Chisel?) -> Verilog

eas lab lab.eas at gmail.com
Sat Dec 28 18:18:42 CET 2013

Interesting: another 2 languages.
Do we want to REMBEMER these syntaxes [ ; ] also?

OTOH the idea of having a VHLL/script calling a low/difficult language,
is effective.  I discovered festival:TextToSpeech which uses `scheme`
a clean/managable scripting language which calls the impossible C++
libraries. I failed to compile the package and had to find an older
pre-compiled version. And was warned that gcc is a monster and a
moving target.

Rather than the lispy/nested notation, I'm fascinated by the
concatenative/compositional notation which *nix:shell achieves;
but with a very messy syntax. So you can say: [I'm just inventing this]
 show me the table of all processes
| but only the lines where colum 3 contains "*mc*"
| and where the colum7 [with the digits reversed] equals colum9
| and ...

This notation has no identifiers' names to remember.
There's only <it>, which was the output from the previous stage.

On 12/26/13, greim <greim at schleibinger.com> wrote:
> Hi ,
> i am very surprised and impressed about the "Oberon 2013 edition" project.
> The future is embedded as you may see for example at all the hype around
> Arduinio and RasperryPi and of course all SmartPhone Aps.
> The problem is that all this embedded devices around are programmed
> mostly by "stupid" electronic engineers (like me for more then 30 years)
> and that the information sciences are focused on the big irons (also a
> modern PC is a big iron) for decades.
> Its a fantastic decision of Professor Wirth to use a FPGA instead of any
> ARM or similar 32bit device!
> The only ugly spot or missing link in this project is the Verilog
> language, but i know that VHDL and Verilog are the only real world tools
> for this job..
> BUT i like to make a hint to the Chisel project
> (http://www.inf.ethz.ch/personal/wirth/ProjectOberon/index.html) .
> They expanded SCALA (an up-polished JAVA) as a front-end for Verilog.
>  From the CHISEL/Scala code they are generating Verilog and C++ code for
> the simulation.
> So porting/making a kind of Chisel to Oberon would be the missing link
> in the whole project.
> So anybody out there knowing both language good enough?
> Is there any chance to do this?
> Regards
> Markus Greim
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon

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