[Oberon] RISC5

[Paul Reed]

Dear Joerg,

> By definition, Project Oberon works on the imaginary RISCv5.
> NW emulated his RISCv5 on an FPGA HW
> PdW emulated the RISCv5 in C and SDL on arbiträry HW
>
> Short: Project Oberon is ALWAYS emulated as there is no real RISCv5 HW.

That's rubbish.  The RISC5 is implemented in hardware.

Thanks,
Paul