[Oberon] RISC5

[Jörg]

Hi Paul

Depends on the definition of "emulated" vs "implemented" :-)

Couldn't you do the following analogy?
 Verliog code  = PdWs emulator code
 Verilog tools = C compiler
 Spartan 3     = host environment

br
Jörg

-----Original Message-----
From: Paul Reed [mailto:paulreed at paddedcell.com] 
Sent: Dienstag, 15. April 2014 15:10
To: ETH Oberon and related systems
Subject: Re: [Oberon] RISC5

Dear Joerg,

> By definition, Project Oberon works on the imaginary RISCv5.
> NW emulated his RISCv5 on an FPGA HW
> PdW emulated the RISCv5 in C and SDL on arbiträry HW
>
> Short: Project Oberon is ALWAYS emulated as there is no real RISCv5 HW.

That's rubbish.  The RISC5 is implemented in hardware.

Thanks,
Paul



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