[Oberon] RISC5

[volkert at nivoba.de]

Am 15.04.2014 15:10, schrieb Paul Reed:
> Dear Joerg,
>
>> By definition, Project Oberon works on the imaginary RISCv5.
>> NW emulated his RISCv5 on an FPGA HW
>> PdW emulated the RISCv5 in C and SDL on arbiträry HW
>>
>> Short: Project Oberon is ALWAYS emulated as there is no real RISCv5 HW.
> That's rubbish.  The RISC5 is implemented in hardware.
>
> Thanks,
> Paul
To Joerg: If "real RISC5 HW means" an ASIC, then yes.

To Paul: I would also say the FPGA emulates the RISC5 behaviour. But the
behaviour is implemented in HW (= FPGA). The RISC5 Model is
described in verilog, it is compiled/synthesized to a FPGA configuration.

One RISC5 Model is described in C, compiled to some target processor 
(x86, ARM).
That is Peter´s Emulator.

But both are "emulations" of the RISC5  .... rubbish? i hope not.

BW,
Volkert