[Oberon] 1G RAM in Emulated RISC Oberon

[Charles Perkins]

I have modified the oberon-risc-emu a little bit more so that I can have a large heap and
more space for modules.

Now I have a 1GB of RAM in my RISC V5 Oberon system.

I have updated my patches for the emulator but I expect to
discard my patches as Peter finds cleaner ways to incorporate the functionality.

Thank you Peter for the alternate framebuffer merging!

Like we said elsewhere, I think its important to keep backwards compatibility with the FPGA risc
image so that we can have a coherent new system. Peter's changes nicely maintain compatibility.

Chuck



On Jun 17, 2014, at 12:28 PM, Peter De Wachter <pdewacht at gmail.com> wrote:

> The bootloader doesn't need to be changed, it still works. The I/O
> registers didn't really move, depending on your point of view: the clock
> was at addres -64 in the original system and with my changes it remains
> at address -64.
> 
> On 17-06-14 17:48, Charles Perkins wrote:
>> Excellent! 
>> 
>> In my changes I had left the bootloader alone but an 'hardware' change such
>> as expanding the address space and moving the IO registers naturally suggests
>> re-linking the bootloader to match. Will you be re-linking 
>> the bootloader for your modified emulator?
>> 
>> In any case I look forward to downloading and working with the revised emulator.
> 
> 
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