[Oberon] Oberon on FPGA - how much does the system "stallx"?

[Davide Della Casa]

Hi,

I'm reading on how Oberon of FPGA manages video generation - the chosen way
is to have SRAM in common between CPU and video system.

So (reading the docs) the "stallx" line is used to arbitrate: "The signal
(wire) dspreq stalls the processor (stallX) and decides whether the memory
address (SRAdr) should be taken from the processor (adr) or the display
controller (vidadr)".

Now I'm wondering what percentage of time does the CPU stall because of
this? Is the CPU only effectively free to work during the "invisible lines"
and "beam reset" times? Or is there significant time available while
"racing the beam"?

Also I'm curious to know whether alternate solutions could potentially be
in the cards to avoid the contention

a) dual port SRAM (too expensive / too many pins needed?)
b) SRAM used in two "blocks" - one dedicated to screen and other so
contention is reduced (too many pins needed?) - potentially with a way for
the CPU to know if the "video" block is available.
c) ...?

(I'd think that such considerations could be worthy of inclusion in the
docs by the way)

Any links welcome about other typical arrangements of interest that are
found in fpga projects "in the wild" in respect to video management...

Cheers,
Davide Della Casa
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