[Oberon] RISC5 / FPGA Architecure and provider

[Walter Gallegos]

Hi group

I read some post about FPGA family, provider and board. In my opinion, think 
this RISC processor with a FPGA architecture and provider in mind is a big 
mistake.

With minor changes, even on the original Verilog sources, this RISC could be 
independent of FPGA architecture. So, could be implemented on any FPGA with 
sufficient resources. As exercise, I translated then Verilog RISC sources to 
MAX10 (Altera) in a couple of hours after implement the testbench; then, 
changing one module same sources could be implemented in Xilinx or Altera.

Thinking in FPGA world, is more attractive have a "general propose" RISC 
core with very basic bus and IO capabilities and leave to the final user add 
your custom functionalities. To mention so classic example, is more 
efficient en terms of resources and power consummation implement a FIR in 
hardware than software.
Hi group

Again in my opinion as FPGA designer, the most timing consuming task could 
be a software environment to support JTAG for downloading and debug and 
custom hardware.

Regards,
Walter