[Oberon] oberonnet of things

[skulski at pas.rochester.edu]

All this would be very nice if it was archived and documented on the web.
I would like to look at the files and think how this stuff could be used.
But where are the files? Is there a repository available somewhere?

Wojtek

> <<< I wouldn't go as far as to claim that - even the most powerful iCE40
> devices have only got 16KBytes of BRAM.
>
> Doesn't your RISC processor use external SRAM? Is there a minimum BRAM
> requirement? I was under the impression we would be using the same flash
> ram chip that populates the FPGA with at startup for the RISC OS, and
> BRAM only holds user space programs (pulled from the flash ram).
>
> I have the Oberon0 RISC system compiling for the ICE40's using the
> IceCube2 IDE. It appears to be able to fit on the 4k and up versions of
> the Ice40's very comfortably. Of coarse, this is the RISC0
> implementation which is surely much different than your RISC5
> implementation.
>
> A dedicated Oberon IoT mini board should realistically be implemented
> directly in Verilog anyway. At some point you go "Shouldn't I just write
> this in Verilog or Lola, at least?". The IoT board should be approached
> this way, right?
>
> <<<Nevertheless, the iCE40 is extremely interesting for one reason alone:
> IceStorm.
>
> IceStorm is indeed very interesting. It brings a simple/understandable HDL
> compiler into the mix. It was Clifford who translated the UCF file, and
> gave me other pointers to get it to compile correctly. I think it took him
> all of 5 minutes to get Oberon compiling.
>
> Regards
>
>
>
>
>
>
>
>
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