[Oberon] FPGA-related Project Oberon Customizations

[Jörg]

Hi

One idea to adopt the RISC5 to a RISC6 is to enlarge the addressable memory
from 1MB to 2MB.
With this increase, color graphics comes within reach...

TCP/IP networking will come this summer, but still based on RISC5 :-) 

br
Jörg

-----Original Message-----
From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
jwr at robrts.net
Sent: Dienstag, 16. Februar 2016 06:59
To: oberon at lists.inf.ethz.ch
Subject: [Oberon] FPGA-related Project Oberon Customizations

What FPGA-related Project Oberon customizations are people considering  
or implementing?

At http://oberonstation.x10.mx/smf/index.php?topic=26.0 I posted some  
questions about how the OberonStation is being used, and what projects  
and ideas others are pondering. My questions can easily be expanded  
beyond the OberonStation, to any and all of the Project Oberon 2013  
implementations. Within Chris Burrows' response, he indicated "The  
opportunities for customising the FPGA hardware are what excites me  
about RISC5 Oberon." That is a particularly interesting observation,  
and I wonder what types of customizations others are considering or  
are already actively implementing?

One possibility includes enhancement of the RISC5 CPU to include  
particular special features. [Given that it's supposed to be a REDUCED  
I.S.C,, which small enhancements would still be desirable?] Other  
possibilities might involve modification of the display to implement  
color graphics, or to use some of the I/O pins to implement a  
different network communication interface.  I'm interested in parallel  
programming, so perhaps some kind of co-processor or multi-core RISC  
instantiation (perhaps requiring movement toward AOS/A2 concepts) is  
of interest.

What particular types of "hardware" modification within the FPGA [i.e.  
implemented primarily via changes to the Verilog code] do you think  
are of interest?

-- John Roberts

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