[Oberon] FPGA-related Project Oberon Customizations

[Douglas G. Danforth]

John,
Your comment about "what customizations are people considering" goads me 
to respond.

Background: I am currently converting "Deep Learning" to Component 
Pascal to understand
what all the excitement is about.

Google AI algorithm masters ancient game of Go 
<http://www.nature.com/news/google-ai-algorithm-masters-ancient-game-of-go-1.19234>

Also

Andy Rubin Unleashed Android on the World. Now Watch Him Do the Same 
With AI 
<http://www.wired.com/2016/02/android-inventor-andy-rubin-playground-artificial-intelligence/> 


Those two stories in the context of Oberon suggests to me that a world 
of "minds"
similar to the internet of things 
<https://en.wikipedia.org/wiki/Internet_of_Things> could be implemented 
on a vast number of devices.
The "collective" would be continually processing and sharing 
information; collected
locally and shared globally.

My background is a mixture of physics and machine learning (speech 
recognition) so
my thoughts tend to run in  those directions.

-Doug Danforth

On 2/15/2016 9:59 PM, jwr at robrts.net wrote:
> What FPGA-related Project Oberon customizations are people considering 
> or implementing?
>
> At http://oberonstation.x10.mx/smf/index.php?topic=26.0 I posted some 
> questions about how the OberonStation is being used, and what projects 
> and ideas others are pondering. My questions can easily be expanded 
> beyond the OberonStation, to any and all of the Project Oberon 2013 
> implementations. Within Chris Burrows' response, he indicated "The 
> opportunities for customising the FPGA hardware are what excites me 
> about RISC5 Oberon." That is a particularly interesting observation, 
> and I wonder what types of customizations others are considering or 
> are already actively implementing?
>
> One possibility includes enhancement of the RISC5 CPU to include 
> particular special features. [Given that it's supposed to be a REDUCED 
> I.S.C,, which small enhancements would still be desirable?] Other 
> possibilities might involve modification of the display to implement 
> color graphics, or to use some of the I/O pins to implement a 
> different network communication interface. I'm interested in parallel 
> programming, so perhaps some kind of co-processor or multi-core RISC 
> instantiation (perhaps requiring movement toward AOS/A2 concepts) is 
> of interest.
>
> What particular types of "hardware" modification within the FPGA [i.e. 
> implemented primarily via changes to the Verilog code] do you think 
> are of interest?
>
> -- John Roberts
>
> -- 
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>

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