[Oberon] RISC5 implementation issues.

[Paul Reed]

Hi Walter,

> So, RISC5 use general propose resources to routing a clock signal.

I agree with Magnus, the tools add the relevant clock buffer as part of
their job, and the source code is kept simple and clear.

FPGAs are a little off-topic for many Oberoners, but hopefully the below
simple hardware LED counter for the Spartan 3 board (easily adapted to
almost any other board!) might be indulged, and interesting for enough
people :)

If you create a project in Xilinx ISE for the xc3s200-4ft256 and add these
source files, then "Generate Programming File", then as far as I can see
from the reports, the tools add the appropriate clock buffers and global
resources - correct me if I'm wrong!

Cheers,
Paul


(test.v)

`timescale 1ns / 1ps

module TestTop(
    input CLK50M,   //50MHz
    output [7:0] leds);

reg clk;
reg [31:0] cnt;

assign leds = cnt[31:24];

always @(posedge clk) //25MHz
  cnt <= cnt + 1;

always @(posedge CLK50M) clk <= ~clk;

endmodule

(test.ucf)

NET "CLK50M" LOC = "T9" ;
NET "leds[0]" LOC = "K12";
NET "leds[1]" LOC = "P14";
NET "leds[2]" LOC = "L12";
NET "leds[3]" LOC = "N14";
NET "leds[4]" LOC = "P13";
NET "leds[5]" LOC = "N12";
NET "leds[6]" LOC = "P12";
NET "leds[7]" LOC = "P11";