[Oberon] RISC5 implementation issues.

[Walter Gallegos]

Hi Paul,

My apologies for this off topic, ProjectOberon is basically a learning 
tool some hardware comments should not be bad.

Yes the tool add the clock buffers because FF clock edge detectors must 
be connected to clock distribution tree, this do no correct the issue.
The problem is, to connect a FF output, as clk signal is, to the clock 
buffer input the signal need be routed by general propose lines and 
interconnection matrix. This generate an uncontrolled delay.
This issue has minor effect in RISC5 because is very special case where 
all project is self contained.

A correct technique could be, RISC5 use a DCM to generate 75MHZ, use the 
same DCM to generate both 25MHZ (CLKDV) and 75MHZ (CLKFX) from 50MHZ 
(CLKIN).

Regards,
Walter


El 2016-02-17 a las 06:39, Paul Reed escribió:
> Hi Walter,
>
>> So, RISC5 use general propose resources to routing a clock signal.
> I agree with Magnus, the tools add the relevant clock buffer as part of
> their job, and the source code is kept simple and clear.
>
> FPGAs are a little off-topic for many Oberoners, but hopefully the below
> simple hardware LED counter for the Spartan 3 board (easily adapted to
> almost any other board!) might be indulged, and interesting for enough
> people :)
>
> If you create a project in Xilinx ISE for the xc3s200-4ft256 and add these
> source files, then "Generate Programming File", then as far as I can see
> from the reports, the tools add the appropriate clock buffers and global
> resources - correct me if I'm wrong!
>
> Cheers,
> Paul
>
>
> (test.v)
>
> `timescale 1ns / 1ps
>
> module TestTop(
>      input CLK50M,   //50MHz
>      output [7:0] leds);
>
> reg clk;
> reg [31:0] cnt;
>
> assign leds = cnt[31:24];
>
> always @(posedge clk) //25MHz
>    cnt <= cnt + 1;
>
> always @(posedge CLK50M) clk <= ~clk;
>
> endmodule
>
> (test.ucf)
>
> NET "CLK50M" LOC = "T9" ;
> NET "leds[0]" LOC = "K12";
> NET "leds[1]" LOC = "P14";
> NET "leds[2]" LOC = "L12";
> NET "leds[3]" LOC = "N14";
> NET "leds[4]" LOC = "P13";
> NET "leds[5]" LOC = "N12";
> NET "leds[6]" LOC = "P12";
> NET "leds[7]" LOC = "P11";
>
>
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>

-- 

Walter Daniel Gallegos
Programmable Logic & Software
Consultoría, Diseño, Entrenamiento.
Montevideo, Uruguay
EMAIL walter at waltergallegos.com
Tel +598 26 23 44 60 | Cel +598 99 18 58 88