[Oberon] RISC5 implementation issues.

[Magnus Karlsson]

On 2/16/2016 11:52 AM, Walter Gallegos wrote:
> Magnus,
>
> /always @ (posedge CLK50M) clk <= ~clk;
>
> /This is also a bad practice.  clk edge are not aligned with CLK50M in 
> a uncontrolled fashion. So, this is a kind of asynchronism for the 
> rest of FPGA.
>
> Walter
>
No, not bad practice at all!

The input signal CLK50M is only used in one place and that is to create 
the signal clk.  The signal clk does not need to be aligned with CLK50M 
in any fashion since it's never used by any logic clocked by CLK50M.
If you believe there is a problem here then point us to the line in the 
code where this problem exist.

Magnus
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