[Oberon] RISC5 implementation issues.
jwr at robrts.net
jwr at robrts.net
Thu Feb 18 01:17:14 CET 2016
Regarding continuing the discussion of FPGA and RISC5 implementation
issues by private email vs on this list vs elsewhere, I for one would
like to have the discussion continue in a somewhat public forum, so
that those of us interested in learning more about the Project Oberon
FPGA implementation and related hardware aspects, as well as more
general FPGA implementation concerns, can follow along and learn.
The insights from Magnus Karlsson and Paul Reed concerning details of
the Project Oberon 2013 implementation are very enlightening, and the
FPGA-related "best practices" communicated so far from Walter Gallegos
and Wojtek Skulski are likewise enlightening and very valuable to
know. I want to read and learn more information in both areas!! And
other related areas also!!
From my perspective, this Oberon List is an appropriate forum. But
if most participants prefer to keep this list focused on Oberon
SOFTWARE, and encourage the HARDWARE-related discussions to take place
elsewhere, that's fine too. Is it easy to set up a parallel hardware
list? [eg oberon-hw at lists.inf.ethz.ch ??] What about using a portion
of the OCP Forum for hardware discussions? I do not know what forum is
preferred, but I do know that I would like to continue to follow
along. My recommendation would be to continue on right here. Thank you!!
-- John Roberts
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