[Oberon] RISC5 implementation issues.

[Lars]

On Wed, February 17, 2016 5:17 pm, jwr at robrts.net wrote:
>

> Regarding continuing the discussion of FPGA and RISC5 implementation
> issues by private email vs on this list vs elsewhere, I for one would like
> to have the discussion continue in a somewhat public forum, so that those
> of us interested in learning more about the Project Oberon FPGA
> implementation and related hardware aspects, as well as more general FPGA
> implementation concerns, can follow along and learn.
>

It's not good to split up lists unless a project is huge. If you split up
a list on a small project it fragments the community.  Oberon is tiny
enough of a project that splitting up the lists generally would be
detrimental, IMO.

In fact the only time I get too much email from oberon list is generally
around talking real world stuff. Other than those times, the email
quantity is very small.