[Oberon] Fast version of Oberon RISC5 for Pepino

[Jörg Straube]

Walter

Magnus rewrote the clock generation according to your recommendation to use DCMs for clock generation and not general logic circuitery.
One question as I'm not at all an expert with clocks: If I look at the FPGA sources of the RS232 drivers, I still find the method that the clock to drive the RS232 is generated by dividing the clk with "normal" circuitery.
Would that be okay for you? Or in other words: why might it be okay there but not for SRAM access? 

br
Jörg

> Am 26.02.2016 um 18:59 schrieb Magnus Karlsson <magnus at saanlima.com>:
> 
> One outcome of the discussion about the Oberon RISC5 verilog code is that I did a deeper study about the clock limits for the project and found that the RISC5 CPU in itself can be clocked at up to about 66 MHz but the external SRAM path is too slow for that speed (read is the problem).  The asynchronous nature of the SRAM interface makes it hard to constrain the ISE compiler to work hard on this path.
> 
> I did trace the SRAM read data path and found that it takes about 10 ns from the SRAM data input pins to the Z register bit (this is the longest path).  The address output path is about 5 nS and with a 10 nS SRAM access time the fastest system clock cycle should be around 25 nS.
> 
> To test this out I created a version of the code that runs the CPU at 37.5 MHz (26.666 nS) instead of 25 MHz, i.e. the CPU is running 1/2 the video clock rate instead of 1/3,  and it seems to run fine of both the LX9 and the LX25 version of Pepino.  All timing constants (UART Rx, UART Tx, SPI and millisecond timer) have been changed to reflect the 50% faster clock rate.
> 
> If anyone want to try it, the project (including bit files) is available here:
> https://github.com/Saanlima/Pepino/tree/master/Projects/RISC5Verilog_Pepino_fast
> 
> Cheers,
> Magnus
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