[Oberon] Fast version of Oberon RISC5 for Pepino

[Walter]

Jörg

In FPGA a clock signal is a signal that toggle the output of a register 
but not the signal that enable to toggle.

Trying to clarify the statement, the D or CE input of a FF can't change 
the Q output by itself. Is the clock edge of interest that toggle Q 
according to D and CE.

This allow toggling all registers between clock skew boundaries. As the 
implementation tool know clock distribution tree skew, PAR try to place 
and route the design to respect setup and hold time of all registers at 
component operational limits.

So, generate a baud rate with a counter and use this counter as CE of 
UART registers if safe.

Walter

On 2/27/2016 6:29 AM, Jörg Straube wrote:
> Walter
>
> Magnus rewrote the clock generation according to your recommendation to use DCMs for clock generation and not general logic circuitery.
> One question as I'm not at all an expert with clocks: If I look at the FPGA sources of the RS232 drivers, I still find the method that the clock to drive the RS232 is generated by dividing the clk with "normal" circuitery.
> Would that be okay for you? Or in other words: why might it be okay there but not for SRAM access?
>
> br
> Jörg
>