[Oberon] FPGA Portability

[Walter Gallegos]

My experience writing HDL to the industrial world is that portability in 
FPGA is more a myth than a reality. With the FPGAs available today is 
impossible build an efficient project without create some portability 
issues.

Inference "works", but not all times; FPGA architecture, tools versions 
and setting play your role also. I infer components some times but 
inference must be handled knowing what you are doing.

Writing in HDL without taken in care how the hardware description will 
be implemented into the resources available in the FPGA is the one of 
the most biggest mistakes that you can do. Believe or not, forgetting 
the hardware when you are describing hardware  is one of the most common 
sources of issues found in consultancy, as write in HDL as in a software 
language.

When you need push a design to the limits use 4 inputs LUTs or 6 inputs 
LUT could make a difference. Of course with today FPGAs and frequencies 
under ~50 MHZ in certain cases you can take some liberties and 
unfortunately the project "works". The clock issue was a very 
illustrative example.

About portability, our approach to minimize issues is build a 
personalization package with all non portable resources, then we 
instantiate the components in the package when needed. To porting a 
project to another FPGA architecture only the personalization package 
must be rewrite.

Walter.