[Oberon] Oberon System V5 TRAP facility

[eas lab]

On 4/9/16, thomas.kral at email.cz <thomas.kral at email.cz> wrote:
> Hi,
>
> I have managed to trigger a TRAP condition for the first time on FPGA Oberon
> V5.
>
> I am curious to see some verbatim of the cause, as I read in the books there
> should be a small view displayed with call stack sequence.
>
> Can this functionality be enabled somehow, as I currently only see a TRAP in
> system log viewer?
>
> Many thanks
> Tomas
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