[Oberon] RISC5

[Chris Burrows]

Not such a trivial question as it turns out. It appears that the correct
terminology is RISC-5 not RISC5 as I stated, but it gets more interesting
than that. The evolution of Wirth's RISC design is described in detail in
the paper titled:

"The Design of a RISC Architecture and its Implementation with an FPGA" 

The answer to your question can be found in the summary of the evolution of
the design from RISC-0 to RISC-5 in the introduction. You can download a
copy from the 'TRM and RISC: FPGA-related Work' section of Prof Wirth's
site:

https://www.inf.ethz.ch/personal/wirth/

After re-reading this document I realised that I had misunderstood the
meaning of RISC-5 myself. In fact the Astrobe Embedded Project Oberon system
is more like a RISC-4 system as it does not need the mouse, keyboard or VGA
capabilities. However, it also uses on-chip BRAM (instead of external SRAM)
which is an attribute of the RISC-0 design. Except that it is a von Neumann
Architecture which is an attribute of RISC-2! 

I might just describe it as 'based on Wirth's RISC Architecture' to minimise
any misconceptions ... 

Regards,
Chris

Chris Burrows
CFB Software
http://www.cfbsoftware.com


> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> peter at easthope.ca
> Sent: Sunday, 11 September 2016 12:32 AM
> To: oberon at lists.inf.ethz.ch
> Subject: [Oberon] RISC5; was Embedded Project Oberon on a breadboard
> 
> From:	Chris Burrows <chris at cfbsoftware.com>, Sat, 10 Sep 2016
> 14:54:09 +0930
> > ... ported the Astrobe Embedded Project Oberon RISC5 system ...
> 
> Sorry for a trivial question but I wonder about an acceptable
> statement of the meaning of RISC5.
> "RISC5, the CPU of Project Oberon 2013, implemented in a FPGA."
> What is the significance of "5"?
>