[Oberon] Re (2): RISC5

[peter at easthope.ca]

From:	Chris Burrows <chris at cfbsoftware.com>Sun, 11 Sep 2016 09:32:43 +0930
> ... terminology is RISC-5 not RISC5 ...

Corrected.

> ... in the summary ...
> download a copy from the 'TRM and RISC: FPGA-related Work' 
> section of Prof Wirth's site:
> https://www.inf.ethz.ch/personal/wirth/

Right oh; it's on my reading list.  

> I might just describe it as 'based on Wirth's RISC Architecture' to minimise
> any misconceptions ... 

Changed that also.  "defined by a Verilog text and implemented 
in a FPGA" is wrong?

Wikipedia also lacks an explanation of BRAM.  Block or bridging 
random access?  

Incidentally, a photo of any of the FPGA systems should fit nicely 
in the gallery next to glossary.

Regards,          ... Lyall E.
 
-- 
123456789 123456789 123456789 123456789 123456789 123456789 123456789
Tel +1 360 639 0202 
http://easthope.ca/Peter.html Bcc: peter at easthope. ca