[Oberon] Re (2): RISC5

[Skulski, Wojciech]

> Wikipedia also lacks an explanation of BRAM.  Block or bridging random access?

BRAM means Block RAM. It is Xilinx terminology. Other vendors (Altera, Lattice) name it differently. 

In a nutshell, the FPGA provides several BRAM blocks. Each block is a dual port memory, where ports A and B offer an independent access to the memory content. This is an ideal tool for (for example) video memory, where you can store bitmap with port A, and send it to the video using port B. The ports can use different clock speeds.

The above was just an example. BRAMs can be used in many more ways: FIFOs, buffers, etc..

 Here is excerpt from Xilinx "7 Series FPGAs Memory Resources User Guide". UG473 (v1.11) November 12, 2014.

Page 11: 
The block RAM in Xilinx® 7 series FPGAs stores up to 36 Kbits of data and can be
configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Each 36 Kb block
RAM can be configured as a 64K x 1 (when cascaded with an adjacent 36 Kb block RAM),
32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18, 1K x 36, or 512 x 72 in simple dual-port mode.
Each 18 Kb block RAM can be configured as a 16K x 1, 8K x2 , 4K x 4, 2K x 9, 1K x 18 or
512 x 36 in simple dual-port mode.

Page 13:
Block RAM Introduction
In addition to distributed RAM and high-speed SelectIO™ memory interfaces, 7 series
devices feature a large number of 36 Kb block RAMs. Each 36 Kb block RAM contains two
independently controlled 18 Kb RAMs. Block RAMs are placed in columns, and the total
number of block RAM resources is listed in Table 1-2 by the 7 series device. The 36 Kb
blocks are cascadable to enable a deeper and wider memory implementation, with a
minimal timing penalty.