[Oberon] Re (2): RISC-5; was RISC5

[Pablo Cayuela]

Your welcome Lyall.

In addition to the referenced page that you add to the glossary, I must say
that a better explanation of the RISC-5 processor itself is in the chapters
about the computer in the FPGA version of the book on Project Oberon:

https://www.inf.ethz.ch/personal/wirth/ProjectOberon/PO.Computer.pdf

I can't find the article on google as easy as with "risc-5" but adding
"risc-5 filetype:pdf" it yields on fifth place this one (also in the page
you added to references of glossary):

https://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC-Arch.pdf

In this article by Wirth, RISC-5 is also briefly explained.

Pablo Cayuela


On Mon, Sep 12, 2016 at 10:36 AM, <peter at easthope.ca> wrote:

> From:   Pablo Cayuela <pablo.cayuela at gmail.com>, Sat, 10 Sep 2016
> 19:46:12 -0300
> > You could check Wirth's RISC versions here:
> > https://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC.pdf
>
> Thanks Pablo.  The glossary entry in https://en.wikipedia.org/wiki/
> Oberon_%28operating_system%29
> now has the directory.  Googling "risc-5" yields the article as the third
> result
> with the extract including "RISC-5".
>
>                                         ... Lyall E.
>
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