[Oberon] Oberon-2 on FPGA

[Jörg Straube]

Hi Peter

I'm not the HW freak, more into SW. I'm just wondering whether the memory on the MIST board is the right one
- NWs RISC5 uses a 32 bit architecture. The 1 MB of the RISC5 is addressed as 256K x 32
- The MIST board seems to have 32 MB (generally okay) but seens to be organized as 16M x 16 instead of 8M x 32.

Would that work?

Jörg



Gruss. Jörg
> Am 27.10.2016 um 20:01 schrieb Peter Matthias <PeterMatthias at web.de>:
> 
> 
> 
>> Am 26.10.2016 um 22:33 schrieb Skulski, Wojciech:
>> Peter:
>> 
>> In principle I do not disagree.
>> 
>> http://opencores.org/project,hf-risc
>> 
>> The devil is in the details. The RISC-V project is aiming at a much bigger goal than N.Wirth is aiming at. NW wants "as simple as possible", what translates into a small design which can fit into a small FPGA such as LX9. The only difficulty is the amount of memory. One meg can only support a bare bone system with monochrome graphics. In order to run a meaningful Oberon System with 8-bit graphics, either Linz V4 or System 3, we need about 8 megs. It implies upgrading the memory chips. Otherwise we are fine.
> 
> RISC5 aims at education, RISC-V also at usage. I don't see this as disadvantage. Obviously finished RISC-V CPU FPGA designs already exist.
> 
>> RISC-V is aiming at knocking down ARM. It is a big goal. If you look at lowRISC.org, you will see that they start with Artix-100, because they are not really interested in lean low cost systems. You will see Linux on day one. You will see Chisel, Vivado, and other such high end tools. None of this is small.
> 
> lowRISC wants to put RISC-V in silicon. I don't see it as disadvantage to _additionally_ have other CPU designs in silicon. The RISC-V people have the problem that /their/ OS requires complex support of the core.
> 
>> Staying with RISC5 means small and affordable. Going with RISC-V means taking part in a larger crusade, whose goal is to shake up the entire industry. I think that it is a noble goal to give ARM a little bit of competition. This is why you are seeing Google pouring money into RISC-V. It is good. I appreciate that you are working on the Oberon-2 compiler for the RISC-V target. But let's not make a mistake thinking that RISC-V is meant to be small.
> 
> What's the gate count RISC5 vs. RISC-V? Does RISC5 fit in choosen FPGA while RISC-V does not?
> 
>> I am attracted to the idea of using RISC5 which can fit into a $20 chip. It would be nice to have the Oberon-2 compiler available for this soft core.
>> 
>> Feel free to disagree ;-)
> 
> If RISC5 fits in given FPGA while RISC-V does not, I fully agree. Personally I am only interested in bare metal FPGA Oberon if it would run on this box: https://github.com/mist-devel/mist-board/wiki , independently of the used instruction set. Oberon on RISC-V only exists because I think RISC-V will be used widely in future and because it is a nice intermediate step on the way from MIPS to AARCH64. The instruction set is just about in between.
> 
> Peter
>> 
>> W.
>> ________________________________________
>> From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Peter Matthias [PeterMatthias at web.de]
>> Sent: Wednesday, October 26, 2016 3:21 PM
>> To: oberon at lists.inf.ethz.ch
>> Subject: [Oberon] Oberon-2 on FPGA was: Re:  Oberon for a C++ user.
>> 
>>> Am 26.10.2016 um 17:32 schrieb Skulski, Wojciech:
>>> Meanwhile even Oberon-2 on the FPGA looks remote ;-(
>> 
>> Can't agree here. Oberon-2 for RISC-V exists. RISC-V on FPGA exists.
>> Someone would only have to combine the two ;-)
>> 
>> Peter
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