[Oberon] Oberon-2 on FPGA

Fri Oct 28 17:12:06 CEST 2016

I completely agree.  The MIST guys ported the code for a Mackintosh 
clone for this board and wrote an SDRAM controller that makes the SDRAM 
look like SRAM (the kind of RAM that both the Mac and RISC5 uses).  The 
best they could do is 16-bit access at 8 MHz, far from the 32-bit 25 MHz 
access that RISC5 is currently doing.

AFAIK, there are only two board available on the market that meets or 
exceeds all hardware requirements of RISC5 - OberonStation and Pepino, 
and both run RISC5/Oberon right out of the box.
(http://www.saanlima.com/pepino/index.php?title=Welcome_to_Pepino).

Magnus

On 10/28/2016 7:19 AM, Skulski, Wojciech wrote:
> Joerg:
>
>    in my opinion yes, MIST should be OK in principle. However, the devil is in the details.
>
> 1. Running the 16-bit memory as 32 bits requires a memory controller to read two 16-bit words on every access. It means firmware. There are many FW "memory controllers" doing this, for example on Open Cores. Was one of these chosen by the MIST authors? Was it tested? Keep in mind it is a sizeable piece of FW whose timing is critical.
>
> 2. If you want to run video on this board, was the video controller FW integrated with other FW? Was it tested?
>
> 3. How much FW work you will have to do yourself before you have an Oberon System running on a particular board? Will the authors help?
>
> 4. The authors provide some several FW configurations for this board. Do you feel like taking one of these and modifying it, using the FW development tools? Are you fluent with the FW development process?
>
> 5. Do not underestimate the FW development effort. Look at the dates in the NW firmware files. These dates go back several years. It means that NW himself put quite a bit of time into his seemingly simple firmware. Yours will not be any easier.
>
> I would also recommend having a look at Pipistrello and Oberon Station because the authors have already contributed to this community. Their continuing support is more likely than the MIST support. If I were you, I would talk to the board authors before committing to a particular board.
>
> Both MIST and Pipistrello were initially designed for other uses. An Oberon-specific board may be more appropriate, such as the Oberon Station or other forthcoming boards. In any case, you need to carefully match the HW available on these boards with your projected use. Do not underestimate the FW work which you will put into the project. FW is not like SW, as Walter mentioned yesterday. Even the present RISC5 needs a bit of fine tuning(without touching its instructions), not to mention all the other pieces like memory controller or video controller.
>
> W.
> ________________________________________
> From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Jörg Straube [joerg.straube at iaeth.ch]
> Sent: Friday, October 28, 2016 2:20 AM
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] Oberon-2 on FPGA
>
> Hi Peter
>
> I'm not the HW freak, more into SW. I'm just wondering whether the memory on the MIST board is the right one
> - NWs RISC5 uses a 32 bit architecture. The 1 MB of the RISC5 is addressed as 256K x 32
> - The MIST board seems to have 32 MB (generally okay) but seens to be organized as 16M x 16 instead of 8M x 32.
>
> Would that work?
>
> Jörg
>
>
>
> Gruss. Jörg
>> Am 27.10.2016 um 20:01 schrieb Peter Matthias <PeterMatthias at web.de>:
>>
>>
>>
>>> Am 26.10.2016 um 22:33 schrieb Skulski, Wojciech:
>>> Peter:
>>>
>>> In principle I do not disagree.
>>>
>>> https://urldefense.proofpoint.com/v2/url?u=http-3A__opencores.org_project-2Chf-2Drisc&d=CwIGaQ&c=kbmfwr1Yojg42sGEpaQh5ofMHBeTl9EI2eaqQZhHbOU&r=uUiA_zLpwaGJIlq-_BM9w1wVOuyqPwHi3XzJRa-ybV0&m=GdCwTC2mFYedTdLMWgTXWc1L56xPyDj8n4KbI6B1N5w&s=ZDXohKSNY-xL2kdU_vl5Jq-ASQvFdLQdLDFYOMub7o8&e=
>>>
>>> The devil is in the details. The RISC-V project is aiming at a much bigger goal than N.Wirth is aiming at. NW wants "as simple as possible", what translates into a small design which can fit into a small FPGA such as LX9. The only difficulty is the amount of memory. One meg can only support a bare bone system with monochrome graphics. In order to run a meaningful Oberon System with 8-bit graphics, either Linz V4 or System 3, we need about 8 megs. It implies upgrading the memory chips. Otherwise we are fine.
>> RISC5 aims at education, RISC-V also at usage. I don't see this as disadvantage. Obviously finished RISC-V CPU FPGA designs already exist.
>>
>>> RISC-V is aiming at knocking down ARM. It is a big goal. If you look at lowRISC.org, you will see that they start with Artix-100, because they are not really interested in lean low cost systems. You will see Linux on day one. You will see Chisel, Vivado, and other such high end tools. None of this is small.
>> lowRISC wants to put RISC-V in silicon. I don't see it as disadvantage to _additionally_ have other CPU designs in silicon. The RISC-V people have the problem that /their/ OS requires complex support of the core.
>>
>>> Staying with RISC5 means small and affordable. Going with RISC-V means taking part in a larger crusade, whose goal is to shake up the entire industry. I think that it is a noble goal to give ARM a little bit of competition. This is why you are seeing Google pouring money into RISC-V. It is good. I appreciate that you are working on the Oberon-2 compiler for the RISC-V target. But let's not make a mistake thinking that RISC-V is meant to be small.
>> What's the gate count RISC5 vs. RISC-V? Does RISC5 fit in choosen FPGA while RISC-V does not?
>>
>>> I am attracted to the idea of using RISC5 which can fit into a $20 chip. It would be nice to have the Oberon-2 compiler available for this soft core.
>>>
>>> Feel free to disagree ;-)
>> If RISC5 fits in given FPGA while RISC-V does not, I fully agree. Personally I am only interested in bare metal FPGA Oberon if it would run on this box: https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_mist-2Ddevel_mist-2Dboard_wiki&d=CwIGaQ&c=kbmfwr1Yojg42sGEpaQh5ofMHBeTl9EI2eaqQZhHbOU&r=uUiA_zLpwaGJIlq-_BM9w1wVOuyqPwHi3XzJRa-ybV0&m=GdCwTC2mFYedTdLMWgTXWc1L56xPyDj8n4KbI6B1N5w&s=6FLMKjlmn9OfckVU85z2vLnmlVRdqb04iovsI_dhkgk&e=  , independently of the used instruction set. Oberon on RISC-V only exists because I think RISC-V will be used widely in future and because it is a nice intermediate step on the way from MIPS to AARCH64. The instruction set is just about in between.
>>
>> Peter
>>> W.
>>> ________________________________________
>>> From: Oberon [oberon-bounces at lists.inf.ethz.ch] on behalf of Peter Matthias [PeterMatthias at web.de]
>>> Sent: Wednesday, October 26, 2016 3:21 PM
>>> To: oberon at lists.inf.ethz.ch
>>> Subject: [Oberon] Oberon-2 on FPGA was: Re:  Oberon for a C++ user.
>>>
>>>> Am 26.10.2016 um 17:32 schrieb Skulski, Wojciech:
>>>> Meanwhile even Oberon-2 on the FPGA looks remote ;-(
>>> Can't agree here. Oberon-2 for RISC-V exists. RISC-V on FPGA exists.
>>> Someone would only have to combine the two ;-)
>>>
>>> Peter
>>> --
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