[Oberon] Oberon-2 on FPGA

[chris]

On Fri, 28 Oct 2016 08:12:06 -0700, Magnus Karlsson wrote:
> I completely agree.  The MIST guys ported the code for a Mackintosh 
> clone for this board and wrote an SDRAM controller that makes the 
> SDRAM look like SRAM (the kind of RAM that both the Mac and RISC5 
> uses).  The best they could do is 16-bit access at 8 MHz, far from 
> the 32-bit 25 MHz access that RISC5 is currently doing.

Something is not right here, I believe. I am pretty sure the early 
Macintosh used 150ns DRAM. The MC68000 has a 16 Bit Data Bus only, so 
16-bit access would be correct there. Problem is that the Mac's display 
was fed from the same DRAM and every 4th cycle or so was used for the 
display controller if I remember correctly. That design does not scale 
well to higher speed or display size.

I don't understand enough of the FPGAs to say what this means in that 
context, I just wanted to add some remarks from a Mac oldtimer.

Greetings, chris