[Oberon] Oberon-2 on FPGA

[Magnus Karlsson]

I'm not sure what you mean by "something not right here". The FPGA 
implementation is quite different from the actual Mac hardware.  The 
SDRAM is used for both ROM, RAM and floppy emulation so it's very 
different from the original Mac.  On the MIST board the SDRAM controller 
is clocked at 65 MHz and it takes a fixed 8 clocks to access the memory, 
resulting in 8.125 MHz access rate.  In other words, the system can 
access the memory at max 8.125 MHz.  This bus bandwidth is then used by 
the CPU, the video system and the floppy emulation. The CPU is also 
clocked at 8.125 MHz.  The original MC68000 takes 4 clocks for 1 
instruction cycle so in normal mode it would access memory at 1/4 of the 
available memory bandwidth.  Video takes up one of the CPU idle clock 
cycles (i.e. it also uses 1/4 of the memory bandwidth), and the floppy 
emulation can take up a cycle as well when needed.

Then there is a turbo mode that allows the CPU to run at about 2.5X 
speed.  This can be done since the FPGA version of the CPU can actually 
run at 1 clock per instruction instead of 4 clocks per instruction, so 
can use up the rest of the memory bandwidth after video and floppy has 
taken it's share.

Hope this makes sense.  For more info see 
https://github.com/mist-devel/mist-board/tree/master/cores/plus_too

Magnus


On 10/28/2016 9:11 AM, chris wrote:
> On Fri, 28 Oct 2016 08:12:06 -0700, Magnus Karlsson wrote:
>> I completely agree.  The MIST guys ported the code for a Mackintosh
>> clone for this board and wrote an SDRAM controller that makes the
>> SDRAM look like SRAM (the kind of RAM that both the Mac and RISC5
>> uses).  The best they could do is 16-bit access at 8 MHz, far from
>> the 32-bit 25 MHz access that RISC5 is currently doing.
> Something is not right here, I believe. I am pretty sure the early
> Macintosh used 150ns DRAM. The MC68000 has a 16 Bit Data Bus only, so
> 16-bit access would be correct there. Problem is that the Mac's display
> was fed from the same DRAM and every 4th cycle or so was used for the
> display controller if I remember correctly. That design does not scale
> well to higher speed or display size.
>
> I don't understand enough of the FPGAs to say what this means in that
> context, I just wanted to add some remarks from a Mac oldtimer.
>
> Greetings, chris
>
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