[Oberon] FPGA - Bit reversal

[Chris Burrows]

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Jörg
> Sent: Saturday, 23 September 2017 4:29 PM
> To: ETH Oberon and related systems
> Subject: Re: [Oberon] FPGA - Bit reversal
> 
> No, I disagree.
> So far Oberon isn t bothered with endianess.
> 

I'm not so sure ...

VAR
  s: SET;
  i: INTEGER;

s := {1,2,3);
i := ORD(s);

What is the value of i?

--
Chris