[Oberon] FPGA - Bit reversal
Jörg
joerg.straube at iaeth.ch
Sat Sep 23 15:03:44 CEST 2017
Chris
I know. ORD() is ‚evil‘ as I wrote in a previous mail. ORD(“S“) is not defined either....
Jörg
Am 23.09.2017 um 14:09 schrieb Chris Burrows <chris at cfbsoftware.com>:
>> -----Original Message-----
>> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
>> Jörg
>> Sent: Saturday, 23 September 2017 4:29 PM
>> To: ETH Oberon and related systems
>> Subject: Re: [Oberon] FPGA - Bit reversal
>>
>> No, I disagree.
>> So far Oberon isn t bothered with endianess.
>>
>
> I'm not so sure ...
>
> VAR
> s: SET;
> i: INTEGER;
>
> s := {1,2,3);
> i := ORD(s);
>
> What is the value of i?
>
> --
> Chris
>
>
>
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
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