[Oberon] FPGA - Boot over serial line

[Tomas Kral]

Hi,

After re-reading chapter 14.1. of PO2013 plus Andreas's
git repo `building-tools', I wish to do an exercise of initial
system boot over serial line. 

My understanding is that asterisked `BootLoad' module is placed in
`prom.mem', wherefrom it is fetched by FPGA logic with Verilog module
PROM, on power-cycle or reset.

module PROM
...
initial $readmemh("../prom.mem", mem);
...
endmodule

The above puts it in FPGA Flash ROM, correct?

But what does `prom.mem' all consist of?
Some h/w registers:
0 - A branch to start
...
24 - Limit of module area
- BootLoad
- Oberon0
- ORC
...?

Can I send some commands over line to Oberon0 module, which is a simple
interpreter as documented in PO2013?

It would be interesting to recreate Oberon0.Mod from what we know it
does accomplish, I am also thinking to enrich it with some test
commands to aid implementing of 4-bit raster ops, if not too silly an
idea?

Many thanks

-- 
Tomas Kral <thomas.kral at email.cz>