[Oberon] FPGA - Boot over serial line

[Chris Burrows]

> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of
> Tomas Kral
> Sent: Tuesday, 10 October 2017 10:59 PM
> To: Oberon@
> Subject: [Oberon] FPGA - Boot over serial line
> 
> Hi,
> 
> After re-reading chapter 14.1. of PO2013 plus Andreas's git repo
> `building-tools', I wish to do an exercise of initial system boot
> over serial line.
> 
> My understanding is that asterisked `BootLoad' module is placed in
> `prom.mem', wherefrom it is fetched by FPGA logic with Verilog module
> PROM, on power-cycle or reset.
> 

See Paul Reed's message in this mailing list:

'Boot procedure FPGA Oberon' (23 Jan 2014)

https://lists.inf.ethz.ch/pipermail/oberon/2014/007014.html

Regards,
Chris Burrows
CFB Software
http://www.astrobe.com/RISC5