[Oberon] FPGA - Boot over serial line

[Magnus Karlsson]

Tomas,

/I am not too sure how to assemble .bmm, I may do with an example in 
speaking terms to Oberon Verilog files./

//The information about .bmm files are available in Data2Mem user guide 
from Xilinx.  You can also do a Data2Mem google search for .bmm examples.

/i.e. how translate the below to make it speak to me also to PO2013 
readers. ////Verilog Coding INIT_fl Example - RAMB16 #(.INIT_fl("file.mem") ...) 
ramb16_0 ( <port mapping>);/

This is an alternative way to instantiate the RAM.  NW/PR use the preferred non-vendor specific way of inferring the RAM.  The code above is a suggestion how to directly instantiate the RAMB16 block RAM in the verilog code so that a .bmm file is generated for future use.  If you want to take this route the you have to edit the file PROM.v and replace the following code

reg [31:0] mem [511: 0];
initial $readmemh("../prom.mem", mem);
always @(posedge clk) data <= mem[adr];

with a direct instantiation of the RAMB16 block as indicated in the guide.  If you don't know how to do that then I suggest you do the research your self or take a different approach. It's not like there is no know solution to your problem - just replace the file prom.mem at the root of the project with your new version and re-synthesize.  This is zero-effort, takes 10 min, you don't have to learn anything related to tools like Data2Mem or how to directly instatiate memory components, and people on this list don't have to spend time educate you in advance Xilinx topics that you really don't need.

Just my 2c...

Magnus

On 10/15/2017 11:13 AM, Tomas Kral wrote:
> On Sun, 15 Oct 2017 09:33:11 -0700
> Magnus Karlsson <magnus at saanlima.com> wrote:
>
>> It will also take .mem files (-bd FILENAME [<.elf>|<.mem>]).
> Hi,
>
> Thank you for bearing with my questions.
>
> I am not too sure how to assemble .bmm, I may do with an example in
> speaking terms to Oberon Verilog files.
>
> i.e. how translate the below to make it speak to me also to PO2013
> readers.
>
>> Verilog Coding INIT_fl Example -
>> RAMB16 #(.INIT_fl("file.mem")
>>             ...)
>> ramb16_0 ( <port mapping>);
> Thank you in advance.
>

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