[Oberon] FPGA - Memory Map

[Jörg]

What about this process:
- Use 4 different shift registers; one for each plane.
- Put the 4 LSBs of those registers to the VGA register for the monitor
- Shift all 4 registers by one bit
- If the registers are empty, fill them from memory: each register from a
different plane.

That’s the theory. In practice, you will have to take care of the proper
timing!!
Filling the 4 registers from memory has to be done in such a way that the
chosen VGA timing is still fulfilled. Might be tricky and you will most
probably need a buffer to do so...

br
Jörg

-----Original Message-----
From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of Tomas
Kral
Sent: Wednesday, December 13, 2017 12:18 PM
To: oberon at lists.inf.ethz.ch
Subject: Re: [Oberon] FPGA - Memory Map

On Mon, 11 Dec 2017 11:15:21 +0000
Paul Reed <paulreed at paddedcell.com> wrote:

> 1101_1111_1111_0000_00 + 000(0_1000_0000_0)xxx_xx =
> 1111_0111_1111_0xxx_xx
> 
> ie byte addresses 0E7F00H-0E7F7FH.
> 
> This is indeed the framebuffer address base = 0E7F00H used by the
> Display module.

Hi Paul, thank you.

A nice explanation, I feel a step further to understanding `VID.v'. I
may correct 1110_0111_1111_0xxx_xx ~ 0E7F00H

I still wonder how to compose RGB output, for four 1-bit stacked frames
as opposed to 4-bit, that I have already.

Each 1-pixel color component needs to be fetched from 4 different
buffers in turn then merged to the output.

-- 
Tomas Kral <thomas.kral at email.cz>
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