[Oberon] FPGA - nRF24L01 `RPI Net' server

[Tomas Kral]

On Wed, 16 May 2018 07:40:22 +0200
Jörg Straube <joerg.straube at iaeth.ch> wrote:

> REPEAT
>   GetRegister(status)
> UNTIL {SENT, MAXRETRY} * status <> {};
> ResetBit;

This is what I actually do in `RF24::Write()', but with delays between
retries over chip MAXRETRY, and coding is not so elegant as above.
Timeouts used for receiving end.

I have discovered that I sometimes miss `ACK' for otherwise CRC good
payload. Which causes `RPI' to retransmit, which fills RX_FIFO with
a duplicate at oberon receiver end.

How can this be rectified?

Please see.

Oberon log
==========

012345678901234567890123456789x rcv-done
 snd-done
 00000040 RX_DR data ready
 00000010 RX_FIFO not empty

012345678901234567890123456789x rcv-done
 00000000 RX_DR no data
 00000010 RX_FIFO not empty

012345678901234567890123456789x rcv-done
 0000000E RX_DR no data
 00000011 RX_FIFO empty


RPI log
=======

Recv: size=31 payload=0123456789012345678901234567890 pipe=0
status 16 <== ACK missed retry
status 16 <== ACK missed retry
status 32
Send: size=31 payload=012345678901234567890123456789x pipe:0 retry:2


-- 
Tomas Kral <thomas.kral at email.cz>