[Oberon] Oberon Digest, Vol 170, Issue 3

Jörg joerg.straube at iaeth.ch
Wed Jul 25 14:48:22 CEST 2018


The board has two entities you might use to run AOS
the ARM processor (Cortex M0+)
the Cyclone FPGA could be programmed to be a Cortex M1 or RISC-5 processor.
 

Run AOS on ARM or port AOS to RISC-5

 

br

Jörg

 

Von: Oberon <oberon-bounces at lists.inf.ethz.ch> im Auftrag von Søren Renner <soren.renner at gmail.com>
Antworten an: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
Datum: Mittwoch, 25. Juli 2018 um 13:51
An: <oberon at lists.inf.ethz.ch>
Betreff: Re: [Oberon] Oberon Digest, Vol 170, Issue 3

 

Is this board going to run Active Oberon (A2 OS)? 

 

On Wed, Jul 25, 2018 at 6:00 AM, <oberon-request at lists.inf.ethz.ch> wrote:

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Today's Topics:

   1. New Hardware for Oberon / Risc-5 ? (greim)
   2. Re: New Hardware for Oberon / Risc-5 ? (J?rg)
   3. RiskFive: New Hardware for Oberon / RISC5 ? (Skulski, Wojciech)
   4. Wanted: Oberon Syntax in TextMate,        Sublime Text or Atom
      Grammar (Treutwein Bernhard)


----------------------------------------------------------------------

Message: 1
Date: Tue, 24 Jul 2018 12:10:45 +0200
From: greim <greim at schleibinger.com>
To: oberon at lists.inf.ethz.ch
Subject: [Oberon] New Hardware for Oberon / Risc-5 ?
Message-ID: <153b9dd9-b20e-b51e-96d9-798a30bf1d2e at schleibinger.com>
Content-Type: text/plain; charset=utf-8; format=flowed

Hello,

Arduinio brought a brand new FPGA board to the market!
Its quite cheap (50 EUR) and seems to have 8 MByte of SRAM

https://store.arduino.cc/arduino-vidor-4000

Not much info yet.
Seems they will build the future software on System Verilog.
And maybe they create also a Verilog dev. platform on the web.
Could imagine that Intel will support it. Their standing in the embedded 
world is friendly spoken quite weak up to now.

But Arduinio was a success story up to now, so I am optimistic that they
will bring FPGA programming to the people, as they did with 
microcontroller programming.

Could any body say if the Cyclone 10CL016 is powerful enough to handle 
the Oberon system?

Bringing Oberon and Arduinio together would be a big step ahead for 
Oberon / Risc-5, I think.

Markus



------------------------------

Message: 2
Date: Tue, 24 Jul 2018 13:27:45 +0200
From: J?rg <joerg.straube at iaeth.ch>
To: <greim at schleibinger.com>
Cc: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
Subject: Re: [Oberon] New Hardware for Oberon / Risc-5 ?
Message-ID: <03084B12-A275-4EC3-8812-02BC57554A96 at iaeth.ch>
Content-Type: text/plain;       charset="UTF-8"

Markus



Comparing FPGAs 1:1 is difficult. The RISC-5 CPU fits in a LX9.

- LX9     has    9K logic cells,   576 kbits memory,   200 IO

- CL016 has 16k logic cells,    504 kbits memory,  340 IO



>From the order of magnitude Oberon should fit



J?rg



?Am 24.07.18, 12:12 schrieb "Oberon im Auftrag von greim" <oberon-bounces at lists.inf.ethz.ch im Auftrag von greim at schleibinger.com>:



    Hello,



    Arduinio brought a brand new FPGA board to the market!

    Its quite cheap (50 EUR) and seems to have 8 MByte of SRAM



    https://store.arduino.cc/arduino-vidor-4000



    Not much info yet.

    Seems they will build the future software on System Verilog.

    And maybe they create also a Verilog dev. platform on the web.

    Could imagine that Intel will support it. Their standing in the embedded 

    world is friendly spoken quite weak up to now.



    But Arduinio was a success story up to now, so I am optimistic that they

    will bring FPGA programming to the people, as they did with 

    microcontroller programming.



    Could any body say if the Cyclone 10CL016 is powerful enough to handle 

    the Oberon system?



    Bringing Oberon and Arduinio together would be a big step ahead for 

    Oberon / Risc-5, I think.



    Markus



    --

    Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems

    https://lists.inf.ethz.ch/mailman/listinfo/oberon







------------------------------

Message: 3
Date: Tue, 24 Jul 2018 12:54:13 +0000
From: "Skulski, Wojciech" <skulski at pas.rochester.edu>
To: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>,
        "greim at schleibinger.com" <greim at schleibinger.com>
Subject: [Oberon] RiskFive: New Hardware for Oberon / RISC5 ?
Message-ID:
        <CY1PR07MB26343995145E1B18C465FE42FF550 at CY1PR07MB2634.namprd07.prod.outlook.com>

Content-Type: text/plain; charset="us-ascii"

All:

Concerning the new hardware, I reworked RiskFive after realizing that the DDR3 memory is bringing significant problems to the system design, such as latencies and caching. So I decided to develop a new version of that board with ZBT RAM. I released the information two days ago on the website RiskFive.com. Today I received the quote for building the "bone" board. This night I finished the motherboard files to be sent for the quote. We will build these boards.

Mind it, RiskFive will be an expensive board. It is meant to be a development platform from which a future board/boards will emerge. For example, there are two 100M Ethernet channels on the motherboard. Obviously, for a practical application you need only one. I am providing two Ethernet chips for the development of two application tiers. Then there is the USB-3 channel for something really fast like data streaming. An interesting spin is that you can map the entire board memory on the USB-3 interface and dump it to the PC. 

A significant goal is the 24 bit color. I provided a professional video DAC rather trying to simulate it with a bunch of el cheapo resistors. The ZBT architecture will allow to develop a very efficient and very simple video channel with 8-bit pixel mapped to 24-bit color via a lookup table (a "palette").

Concerning System Verilog, professor Pong Chu just published his Verilog version of his SOC design book. I received the copy three days ago. It looks magnificent. Highly recommended! Professor Chu is using Artix-7, the exact same chip which I am using on RiskFive. The entire firmware framework is now available from Professor Pong website, both in VHDL and in System Verilog. We do not need to scrounge around for firmware bits and pieces, because a high quality FPro framework is now available. 

My intent is open hardware. The motherboard design files will be released as soon as I actually order this board. The FOM design files will be available in PDF to everyone, and in full source on request. 

Thank you,
Wojtek

------------------------------

Message: 4
Date: Tue, 24 Jul 2018 13:50:05 +0000
From: Treutwein Bernhard
        <Bernhard.Treutwein at Verwaltung.Uni-Muenchen.DE>
To: "'oberon at lists.inf.ethz.ch'" <oberon at lists.inf.ethz.ch>
Subject: [Oberon] Wanted: Oberon Syntax in TextMate,    Sublime Text or
        Atom Grammar
Message-ID:
        <78A8BD6765DCF048A628A51C3FBD1D7659B44E66 at MXS2.zuv.uni-muenchen.de>
Content-Type: text/plain; charset="iso-8859-1"

Does somebody have grammars for 
        Oberon / Oberon-2 / Component Pascal / Active Oberon
as  grammar for
        TextMate / Sublime Text / Atom 


Background: Github wrongly classifies Oberon / Oberon-2 / Component Pascal / Active Oberon
as Modula-2. I opened quite some tiome ago an issue in the github/linguist project
(https://github.com/github/linguist/issues/3888) and they don't accept EBNF grammars.

--
? Bernhard Treutwein


------------------------------

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------------------------------

End of Oberon Digest, Vol 170, Issue 3
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