[Oberon] FPGA - Oberon-7 - Loops

[Andreas Pirklbauer]

   > WHILE <expression> DO S END;
   > REPEAT S UNTIL <expression>;
   > FOR a := <beg> TO <end> BY <inc> DO S END;

1. For the WHILE statement, the official Oberon-7 language definition
specifies that *both* expression evaluation *and* the statement execution
are *repeated* until the boolean expression <expression> yields FALSE.

2. For the REPEAT statement, the official Oberon-7 language definition
does not specify whether expression evaluation is also to be repeated,
in addition to statement execution (which obviously is). But the reference
implementation at www.projectoberon.com implements it that way, i.e.
such that *both* expression evaluation *and* the statement execution
are repeated until the boolean expression <expression> yields TRUE.

3. For the FOR statement, the official Oberon-7 language definition
only specifies that the <beg> expression is evaluated *once* at the
beginning, but does not specify whether expression evaluation is
also to be repeated for the <end> expression. But the reference
implementation at www.projectoberon.com implements it that way, i.e.
such that also the <end> expression is evaluated at *every* iteration.

    [this is in contrast to the Oberon-2 FOR loop, where the language
    specification explicitly *specifies* that *both* the <beg> *and* the
    <end> expression are evaluated only once at the beginning].

Thus, the official Oberon-7 language specification leaves a number
of decisions open (i.e. to the implementation). It can be debated
whether this is desirable or not.

-ap