[Oberon] FPGA - Oberon-7 - Loops

[Tomas Kral]

Hi,

I have the two loops,
 
 FOR a0 := a TO a + (h-1)*bpl BY bpl DO
   FOR a1 := a0 TO a0 + (w-1) DIV 8*4 BY 4 DO
   END
 END;

Recoded as `bpl' is now a variable, as such,

 a0 := a; a2 := a + (h-1)*bpl; WHILE a0 <= a2 DO
   a3 := a0 + (w-1) DIV 8*dpt; FOR a1 := a0 TO a3 BY 4 DO
   END; INC(a0, bpl);
 END;

It does not look nice, at the expense of two more vars, but I hope it
gains some performance at least, does it?

-- 
Tomas Kral <thomas.kral at email.cz>