[Oberon] Cheap chinese FPGA board - is it usable for PO?

[Paul Reed]

> I do not even know whether or not adding a cache would affect the
> compiler. Can the compiler stay the same with and without the cache?

It should not affect it, that is a common (universal?) design goal for a 
cache (at least until RowHammer!).

But it does dramatically decrease predictability and increase 
complexity, violating two of the stated goals of Project Oberon.

Bernhard's suggestion about cheap hardware is very practical, and his 
frustration palpable, but the bigger question is why bother with FPGAs 
at all then, if cost is such an issue?  And does one neglect the value 
of one's time, to learn and maintain this stuff, when it's all a moving 
target?  That cost is FAR larger, even when an implementation already 
exists.

For some people, I'd wager that the FPGA is just in practice an 
immutable platform, which happens to run Oberon, the real object of 
desire.  If you just want such an Oberon system there are many choices 
already, and cheap ARM boards exist to port to - even cheap RISC-V 
boards now.  So now discarding that for a moment, for an FPGA board what 
would be the purpose?

Cheers,
Paul