[Oberon] Cheap chinese FPGA board - is it usable for PO?

[Jörg]

In the easiest form: yes, the compiler stays the same.
If you want to benefit from instruction cache, the compiler could start inlining procedure calls if the procedure’s code fits in the instruction cache. This code optimization is only possible if you adapt the compiler.
Jörg

> Am 11.11.2019 um 18:03 schrieb Skulski, Wojciech <skulski at pas.rochester.edu>:
> 
> 
>> 
>> Indeed cache would help. Feel free to added it to RISC5Top.v (
> 
> I would if I knew how. This is a bit beyond my skill level, even after reading all NW papers from his website.
> 
> I do not even know whether or not adding a cache would affect the compiler. Can the compiler stay the same with and without the cache?
> 
> Wojtek
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon