[Oberon] Oberon on ULX3S explanation

[Paul Reed]

Dear Mr. Emard,

> We have on ULX3S FPGA tried oberon and it works nice
> on 32MB SDRAM at oberon's simple risc CPU, clock 25MHz.

That sounds great!  As most people do not have a ULX3S, might you be 
able to give a brief technical explanation, to describe broadly how it 
was done, which might for example be of help to people who already have 
other FPGA boards which have synchronous DRAM?  It might also help our 
discussions.

Thanks,
Paul Reed