[Oberon] Oberon on ULX3S explanation

[D EMARD]

Compared to DDRx memories, SDRAM's are considered "easy"
to drive, their interface is not very time critical, don't require
special voltage conditions and dedicated signal shaping circuitry
and are typically around 100 verilog lines long that's why they are
so popular on open source FPGA projects

when jumping often to random addresses and fetching small amount
of data each time, they have less latency and thus work are faster than DDRx

Only at long sequential reads then DDRx are faster


On 11/13/19, D EMARD <vordah at gmail.com> wrote:
> Well the SDRAM chips all behave the same so any datasheet
> of micron or alliance would do to see how they "work". At the
> end some deeper understanding is not necessary, there are
> plenty of driver cores in source you can take any one that closest
> fits to your hardware and it will as "black box" expose standard
> interface of data and adress bus with write and read enable signals.
>
>
> On 11/13/19, Skulski, Wojciech <skulski at pas.rochester.edu> wrote:
>> Paul wrote:
>>
>>> Unfortunately, although commonly-used because it's cheap per bit,
>>> synchronous DRAM is much more complicated than the fast asynchronous
>>> static RAM used in the Oberon FPGA reference design.  Getting a
>>> description of how this was implemented on the ULX3S board would have
>>> been useful in understanding the design trade-offs, but unfortunately
>>> all we got was another advert.
>>
>> There are some very good and well documented designs on OpenCores.
>> Whether
>> or not to use them and which one is another matter, but the documentation
>> is
>> worth pursuing.  I do not endorse any of these designs because I have not
>> used them. My recommendation concern the documents. Download, unpack, and
>> read the documents before pursuing any given firmware. Or before
>> designing
>> any board, for that matter. In the past I was guilty of designing boards
>> based on hardware specifications without first looking into firmware
>> issues.
>> Not anymore!
>>
>> http://opencores.org/project,sdr_ctrl  -- 8/16/32 bit SDRAM Controller;
>> 28-page manual
>>
>> http://opencores.org/project,hpdmc -- DDR DRAM targeting video
>>
>> http://opencores.org/project,wbddr3 -- a horror story about DDR3
>>
>> Wojtek
>>
>>
>>
>> --
>> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
>> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>>
>