[Oberon] SDRAM performance

[D EMARD]

eheheee you had same issues buying parts for your boards :))

design issue when I was thinking SDRAM or hypeRAM:

SDRAM: 16 bits 166 MHz
HypeRAM: 8 bits 333 MHz -> 8 wires less but 2x clock higher

as hypeRAM has some logic solved on-chip like internal refresh,
driver core should be be a bit simpler than SDRAM but still would be
a non-trivial core.

it would need additional time critical part: clock domain crossing
logic operating
between 333 MHz RAM and say 50 MHz CPU/video. This should be included
somewhere at cache controller or multiport RAM arbiter I guess.

>From my experience clocking any complex design above 100 MHz in
FPGA is lottery. Very small and simple cores can stand 200 MHz.
For above 300 MHz, just a simple logic - few regs, counters that's all.


On 11/15/19, Skulski, Wojciech <skulski at pas.rochester.edu> wrote:
>
>> Hyperram is nice but take into consideration that only cypress makes them
>> Mouser has them on stock and should be ok for now.
>
> It is true that it is only Cypress. I would expect that other silicon
> vendors will release such parts, but I do not know for sure. There are
> multiple sources  for Cellular RAM.
>
>> On ULX3S the only vendor-specific part was FPGA and last months we have
>> problems getting the parts but we managed,
>
> Happens all the time! I cannot even count the cases when we could not get
> Xilinx FPGAs on time. Same with Analog Devices ADC chips. It is a constant
> hassle.
>
> Wojtek
> --
> Oberon at lists.inf.ethz.ch mailing list for ETH Oberon and related systems
> https://lists.inf.ethz.ch/mailman/listinfo/oberon
>