[Oberon] FPGA RISC byte access

[Paul Reed]

Hi Wojtek,

>     trying to [understand the hardware description] I am now puzzled 
> with the
> individual byte access logic in RISC5 and RISC5top

See also "5.3. Implementing byte-access (RISC-3)" in "The Design of a 
RISC Architecture
and its Implementation with an FPGA":

https://people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC.pdf

HTH,
Paul