[Oberon] QEMU target implementation for Oberon RISC architecture

[Skulski, Wojciech]

Joerg:

saying "RISC processor" do you mean the NW firmware pulled off his website? I am looking at it right now. I do not see "2019" in the Verilog code. How can the real firmware processor respond to the "get version request" which you are describing? It is pretty essential to know the firmware revision, but I do not see it coded verbatim in the actual firmware.

>You can ask the RISC processor to reveal its version with this code

   cpu := SYSTEM.H(2019) MOD 80H;
   IF cpu = 53H THEN       (* RISC5: with interrupts + floating-point, 31.8.2018 *)
   ELSIF cpu = 54H THEN (* RISC5a: no interrupts, no floating-point, 1.9.2018*)
   ELSIF cpu = A0H THEN (* RISC0, 26.12.2013 *)
   END;

W.