[Oberon] QEMU target implementation for Oberon RISC architecture

[Michael Schierl]

Wojtek,


Am 30.12.2019 um 21:11 schrieb Skulski, Wojciech:

> saying "RISC processor" do you mean the NW firmware pulled off his website? I am looking at it right now. I do not see "2019" in the Verilog code. How can the real firmware processor respond to the "get version request" which you are describing? It is pretty essential to know the firmware revision, but I do not see it coded verbatim in the actual firmware.

The compiler function SYSTEM.H only uses the last bit of its operand,
therefore SYSTEM.H(2019) is the same as SYSTEM.H(1).

https://github.com/Spirit-of-Oberon/wirth-personal/blob/master/people.inf.ethz.ch/wirth/ProjectOberon/Sources/ORG.Mod.txt#L984-L987

SYSTEM.H(0) will create a MOV instruction that loads the remainder from
the last division, and SYSTEM.H(1) will create a MOV instruction that
loads the flag register.

Both are implemented in this line of Verilog:

https://github.com/Spirit-of-Oberon/wirth-personal/blob/master/people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RISC5.v#L113

            (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h53}))) :

As you can see, the flag register ends with hexadecimal 53.

You can put anything else in the flag register if you want your
processor to be identified differently.


Regards,


Michael