[Oberon] Oberon OS / HAL / FPGA
paulreed at paddedcell.com
Wed Feb 26 11:19:34 CET 2020
> As a rather new user of Oberon (AOS build 9799) I am interested in
> whether there are really FPGAs on which Oberon runs? Does it have to
> do with the ETH PULP project (http://asic.ethz.ch)?
Not as far as I know.
However, the original Project Oberon system was updated in 2013 and runs
on a variety of FPGA boards.
These boards come and go, and the effort to port the system to a new
FPGA board is relatively high. Currently there is no low-cost
mass-produced board available.
The reference design is based on a Digilent Spartan 3 board, with a
Xilinx Spartan 3 (xc3s200) and 1MB (2 x 256K x 16) external 10ns
asynchronous static RAM. This kind of memory is rare on FPGA boards;
they tend to have much slower (in the random case) but bigger and more
complex synchronous dynamic RAM.
The soft processor is a simple 32-bit RISC designed by Niklaus Wirth.
The instruction set architecture description fits on one sheet of paper.
See http://www.projectoberon.com and Prof. Wirth's home page at
More information about the Oberon