[Oberon] Oberon OS / HAL / FPGA

Joerg joerg.straube at iaeth.ch
Wed Feb 26 13:20:40 CET 2020

Hi Daniel

I run ProjectOberon on this FPGA (Spartan-6 based)


-----Original Message-----
From: Oberon <oberon-bounces at lists.inf.ethz.ch> On Behalf Of Paul Reed
Sent: Wednesday, February 26, 2020 11:20 AM
To: ETH Oberon and related systems <oberon at lists.inf.ethz.ch>
Subject: Re: [Oberon] Oberon OS / HAL / FPGA

Hi Daniel,

> As a rather new user of Oberon (AOS build 9799) I am interested in 
> whether there are really FPGAs on which Oberon runs? Does it have to 
> do with the ETH PULP project (http://asic.ethz.ch)?

Not as far as I know.

However, the original Project Oberon system was updated in 2013 and runs on
a variety of FPGA boards.

These boards come and go, and the effort to port the system to a new FPGA
board is relatively high.  Currently there is no low-cost mass-produced
board available.

The reference design is based on a Digilent Spartan 3 board, with a Xilinx
Spartan 3 (xc3s200) and 1MB (2 x 256K x 16) external 10ns asynchronous
static RAM.  This kind of memory is rare on FPGA boards; they tend to have
much slower (in the random case) but bigger and more complex synchronous
dynamic RAM.

The soft processor is a simple 32-bit RISC designed by Niklaus Wirth.  
The instruction set architecture description fits on one sheet of paper.

See http://www.projectoberon.com and Prof. Wirth's home page at

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