[Oberon] FW: Integrating the Arm Cortex-M3 in a Xilinx FPGA

Skulski, Wojciech skulski at pas.rochester.edu
Tue Mar 31 19:53:52 CEST 2020

FYI. This may interest Chris. In principle, his compiler may lead into an alternative FPGA Oberon System running on the M3 core.

From: Xilinx, Inc. [xilinxmail at xilinx.com]
Sent: Tuesday, March 31, 2020 12:01 PM
To: Skulski, Wojciech
Subject: Integrating the Arm Cortex-M3 in a Xilinx FPGA


Integrating the Arm Cortex-M3 in a Xilinx FPGA

[Xilinx Doulos ARM Cortex-M3 Webinar]

April 8, 2020 | 10 ‒ 11am PDT – Accessible World-Wide

The combination of the widely acclaimed Arm® Cortex®-M MCU architecture with the performance of a Xilinx® FPGA provides more flexibility and greater scope for innovation in the creation of application-optimized designs.

In this webinar, we will examine the Cortex-M3 IP block and discuss its integration inside a Xilinx FPGA.

You will learn about:

  *   The two main system buses, their use model and restrictions
  *   The operations of the Nested Vectored Interrupt Controller (NVIC) and its interaction with a Wakeup Interrupt Controller (WIC)
  *   The memory management operations along with invasive and non-invasive debugging features of the core

Xilinx Authorized Training Provider Doulos presents this webinar with interactive Q&A for the attendees.


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