[Oberon] FW: Integrating the Arm Cortex-M3 in a Xilinx FPGA

[Chris Burrows]

As far as I can see that would only make sense if the RISC5 softcore processor and its Oberon compiler did not already exist. 

>From the benchmarks I have run the overall performance of RISC5 is comparable to a Cortex-M3 MCU running at the same clock speed. However, the RISC5 is much better with floating point code. This runs about 10 times faster on the RISC5 than Cortex-M3 as the M3 doesn't have any FP instructions. 

Also the RISC5 code generator for the Oberon compiler is much simpler than the Cortex-M3 code generator as the RISC5 instruction set is much simpler than the Thumb-2 instruction set used by the Cortex-M3. RISC5 only contains the instructions that are necessary and sufficient to implement the Oberon compiler.

Why bother with an alternative if it is inferior. Or am I missing something? 

Regards,
Chris

Chris Burrows
https://www.astrobe.com


> -----Original Message-----
> From: Oberon [mailto:oberon-bounces at lists.inf.ethz.ch] On Behalf Of Skulski,
> Wojciech
> Sent: Wednesday, 1 April 2020 4:24 AM
> To: oberon at lists.inf.ethz.ch
> Subject: [Oberon] FW: Integrating the Arm Cortex-M3 in a Xilinx FPGA
> 
> FYI. This may interest Chris. In principle, his compiler may lead into an
> alternative FPGA Oberon System running on the M3 core.
> 
> https://www.doulos.com/content/events/Arm_Cortex-M3_Xilinx_FPGA_xlx.php
> ________________________________________
> From: Xilinx, Inc. [xilinxmail at xilinx.com]
> Sent: Tuesday, March 31, 2020 12:01 PM
> To: Skulski, Wojciech
> Subject: Integrating the Arm Cortex-M3 in a Xilinx FPGA
> 
> WEBINAR
> 
> Integrating the Arm Cortex-M3 in a Xilinx FPGA
> 
> [Xilinx Doulos ARM Cortex-M3 Webinar]
> 
> April 8, 2020 | 10 ? 11am PDT   Accessible World-Wide
> 
> The combination of the widely acclaimed Arm  Cortex -M MCU architecture with
> the performance of a Xilinx  FPGA provides more flexibility and greater scope
> for innovation in the creation of application-optimized designs.
> 
> In this webinar, we will examine the Cortex-M3 IP block and discuss its
> integration inside a Xilinx FPGA.
> 
> 
> You will learn about:
> 
>   *   The two main system buses, their use model and restrictions
>   *   The operations of the Nested Vectored Interrupt Controller (NVIC) and
> its interaction with a Wakeup Interrupt Controller (WIC)
>   *   The memory management operations along with invasive and non-invasive
> debugging features of the core
> 
> Xilinx Authorized Training Provider Doulos presents this webinar with
> interactive Q&A for the attendees.
> 
> https://www.doulos.com/content/events/Arm_Cortex-M3_Xilinx_FPGA_xlx.php
> --
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