[Oberon] Unlimited Oberon System for any board

Andreas Pirklbauer andreas_pirklbauer at yahoo.com
Fri May 8 16:41:30 CEST 2020

Hi Paul,

    > So you have hit the nail on the head: to those who wish
    > to turn RISC5 into RISC-V, I plead: use RISC-V.

Exactly!  Either pure RISC5 or straight to RISC-V.

RISC-V is of course not as “simple” as RISC5, but still, it’s a huge
improvement when compared with ARM, Intel, etc. And it’s an ISA I
can actually understand. I have followed the effort at Berkeley
for about a decade now. Although they got a couple of (smaller)
thins wrong (the froze the architecture too soon), it has potential.

I have actually conducted a small experiment and ported (parts of)
the Oberon-07 and my Revised Oberon-2 backend to RISC-V. The
result was: OVG (code generator for RISC-V) is about 1500 lines,
which compares to about 1000 for ORG (for RISC5). So not so bad.
It’s not complete though and would need some work. PS: Also, I
used a somewhat different approach than the compiler from
http://oberon.wikidot.com/oberon-linux-revival-olr (e.g. for fixup
chains), but there also are some similarities.

More information about the Oberon mailing list